RXDPHY_CKEN=Val_0x0, PLLREF_CKEN=Val_0x0, TXDPHY_CKEN=Val_0x0, BYPASS_CKEN=Val_0x0
MIPI-DPHY Clock Enable Register
| TXDPHY_CKEN | Enable configure clock for TX D-PHY 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| RXDPHY_CKEN | Enable configure clock for RX D-PHY 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| PLLREF_CKEN | Enable reference clock for MIPI D-PHY PLL 0 (Val_0x0): Disable clock 1 (Val_0x1): Enable clock |
| BYPASS_CKEN | Enable bypass clock for MIPI D-PHY PLL 0 (Val_0x0): Disable bypass clock 1 (Val_0x1): Enable bypass clock |